Microprocessor Verification using RT-Level Static Analysis Techniques

We present a technique for automatic verification of pipelined microprocessors using model checking. Antecedent conditioned slicing is an efficient abstraction technique for hardware designs at the Register Transfer Level (RTL). Antecedent conditioned slicing prunes the verification state space, using information from the antecedent of a given LTL property. In this work, we model instructions of a pipelined processor into LTL properties, such that the instruction opcode forms the antecedent. We use antecedent conditioned slicing to decompose the problem space of pipelined processor verification on an instruction by instruction basis. We pass the resulting smaller, tractable problems through several lower level verification engines. We thereby verify that every instruction behaves according to the specification and ensure that non-target registers are not modified by the instruction. We use several Boolean level verification engines that use different algorithms to verify all the instruction classes of a Verilog RTL implementation of the OR1200, an off-the-shelf pipelined processor.